Efficient Processing of Neuro-Symbolic AI: A Tutorial and Co-Design Case Study


Zishen Wan1, Che-Kai Liu1, Hanchen Yang1, Ritik Raj1, Jiayi Qian1, Ananda Samajdar2,
Arijit Raychowdhury1, Tushar Krishna1
1Georgia Institute of Technology, 2IBM Research

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Abstract

Neuro-symbolic AI presents an emerging compositional paradigm that fuses neural learning with symbolic reasoning and probabilistic inference to enhance the transparency, interpretability, and trustworthiness of AI solutions for complex real-world tasks. However, achieving real-time, energy-efficient, and scalable deployment of neuro-symbolic intelligence requires cross-disciplinary integration through application discovery, systems thinking, and co-design intelligence.

We take a vertically-integrated approach to enabling efficient and scalable neuro-symbolic computing, from workload benchmarking, hardware architecture, to FPGA prototyping and SoC tapeout [NeuS'25]. First, we conduct workload characterization to uncover key system behavior of neuro-symbolic [ISPASS'24] and compositional LLM-symbolic-probabilistic [ASPLOS'26] models. Second, we build reconfigurable processing unit and dataflow architecture for neuro-symbolic computing [HPCA'25]. Third, we develop end-to-end framework with automated architecture generator for agile neuro-symbolic FPGA deployment [DAC'25]. Finally, we tape out a 40nm programmable heterogeneous SoC chip with integrated RRAM/SRAM datapath, scheduler-informed power management, and programming support for neuro-symbolic AI models. Through this synergistic cross-layer co-design, we demonstrate the feasibility of deploying efficient neuro-symbolic cognitive systems at scale.

We also explore employing neuro-symbolic computing in embodied AI systems by integrating high-level planning-reasoning and low-level perception-control modules. Through system characterization [ISPASS'25] and development of dual memory system, hierarchical cooperation, and heterogeneous SoC architecture [ASPLOS'25], we aim to build more efficient and intelligent human-cognition-like physical AI systems that can better perceive, understand, reason, and interact with the complex real world.

Related Papers

 Efficient Processing of Neuro-Symbolic AI: A Tutorial and Co-Design Case Study
Zishen Wan, Che-Kai Liu, Hanchen Yang, Ritik Raj, Arijit Raychowdhury, Tushar Krishna
International Conference on Neuro-symbolic Systems (NeuS), 2025
Selected as Oral Presentation
Paper

This work presents our vertically integrated approach to enabling efficient and scalable neuro-symbolic computing—spanning workload benchmarking, hardware architecture, FPGA prototyping, and SoC tapeout. Through this cross-layer design, we demonstrate the feasibility of neuro-symbolic cognitive systems at scale.

Workload Characterization

 Towards Cognitive AI Systems: Workload and Characterization of Neuro-Symbolic AI
Zishen Wan, Che-Kai Liu, Hanchen Yang, Ritik Raj, Chaojian Li, Haoran You, Yonggan Fu, Cheng Wan, Ananda Samajdar, Yingyan (Celine) Lin, Tushar Krishna, Arijit Raychowdhury
IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2024
Best Poster Award, DARPA SRC JUMP2.0 CoCoSys Center 2024
Paper / Slide / Media

We systematically categorize neuro-symbolic AI workloads, conduct workload characterizations across hardware platforms, and identify cross-layer optimization opportunities for neuro-symbolic systems.

Hardware Architecture

 CogSys: Efficient and Scalable Neurosymbolic Cognition System via Algorithm-Hardware Co-Design
Zishen Wan*, Hanchen Yang*, Ritik Raj*, Che-Kai Liu, Ananda Samajdar, Arijit Raychowdhury, Tushar Krishna
International Symposium on High-Performance Computer Architecture (HPCA), 2025
Best Paper Award, DARPA SRC JUMP 2.0, 2024
Paper / Slide / Slide (long version) / Poster / Media

We propose CogSys, a characterization and co-design framework dedicated to neurosymbolic AI system acceleration, aiming to win both reasoning efficiency and scalability.
NSFlow: An End-to-End FPGA Framework with Scalable Dataflow Architecture for Neuro-Symbolic AI
Hanchen Yang*, Zishen Wan*, Ritik Raj, Joongun Park, Ziwei Li, Ananda Samajdar, Arijit Raychowdhury, Tushar Krishna
ACM/IEEE Design Automation Conference (DAC), 2025
Paper / Slide

We propose NSFlow, an FPGA framework for efficient, scalable, and adaptive across neuro-symbolic systems. NSFlow features a design architecture generator that identifies workload data dependencies and creates dataflow architectures, as well as reconfigurable array with flexible compute units and re-organizable memory.


Towards Efficient Neuro-Symbolic AI: From Workload Characterization to Hardware Architecture
Zishen Wan, Che-Kai Liu, Hanchen Yang, Ritik Raj, Chaojian Li, Haoran You, Yonggan Fu, Cheng Wan, Sixu Li, Youbin Kim, Ananda Samajdar, Yingyan (Celine) Lin, Mohamed Ibrahim, Jan M. Rabaey, Tushar Krishna, Arijit Raychowdhury
IEEE Transactions on Circuits and Systems for Artificial Intelligence (TCASAI), 2024
Best Paper Award, DARPA SRC JUMP 2.0, 2024
Paper / Fortune News / CoCoSys News

We analyze the neuro-symbolic workload characteristics, and present a hardware acceleration case study for vector-symbolic architecture to improve the performance, efficiency, and scalability of neuro-symbolic computing.
H3DFACT: Heterogeneous 3D Integrated CIM for Factorization with Holographic Perceptual Representations
Zishen Wan*, Che-Kai Liu*, Mohamed Ibrahim, Hanchen Yang, Samuel Spetalnick, Tushar Krishna, Arijit Raychowdhury
Design, Automation and Test in Europe Conference (DATE), 2024
Best Presentation Award, SRC TECHCON 2024
Paper / Slide / SRC News / GT News

We present H3DFACT, the first heterogeneous 3D integrated in-memory compute engine capable of efficiently factorizing high-dimensional holographic representations towards next-generative cognitive AI.
Neuro-Symbolic Architecture Meets Large Language Models: A Memory-Centric Perspective
Mohamed Ibrahim, Zishen Wan, Haitong Li, Priyadarshini Panda, Tushar Krishna, Pentti Kanerva, Yiran Chen, Arijit Raychowdhury
ACM/IEEE Embedded Systems Week (ESWEEK), 2024
Paper / Slide

We analyze the computational challenges of integrating LLMs and neuro-symbolic architecture, and explore state-of-the-art solutions, focusing on the memory-centric computing principles at both algorithmic and hardware levels.

Embodied System Deployment

 ReCA: Integrated Acceleration for Real-Time and Efficient Cooperative Embodied Autonomous Agents
Zishen Wan, Yuhang Du, Mohamed Ibrahim, Jiayi Qian, Jason Jabbour, Yang (Katie) Zhao, Tushar Krishna, Arijit Raychowdhury, Vijay Janapa Reddi
ACM Inter Conf on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2025
Selected as IAP Highlight
Paper / Slide / Slide (long version) / Poster

We propose ReCA, a characterization and system-architecture co-design framework dedicated to cooperative embodied AI agent system acceleration, aiming to enhance both long-horizon multi-objective planning task efficiency and system scalability.


Generative AI in Embodied Systems: System-Level Analysis of Performance, Efficiency and Scalability
Zishen Wan, Jiayi Qian, Yuhang Du, Jason Jabbour, Yilun Du, Yang (Katie) Zhao, Arijit Raychowdhury, Tushar Krishna, Vijay Janapa Reddi
IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2025
Paper / Slide

This paper systematically categorizes the workload characteristics of embodied agent systems and presents a benchmark suite to evaluate their task performance and system efficiency, and suggests system optimization strategies to improve the performance, efficiency, and scalability of future embodied system design.


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Acknowledgments

This work was supported in part by CoCoSys, one of seven centers in JUMP 2.0, a Semiconductor Research Corporation (SRC) program sponsored by DARPA.

© Zishen Wan 2025